As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency in modern electronics, integrated circuits are continuously being reduced in size. To facilitate this size reduction, the sizes of the constituent features, such as electrical devices and interconnect line widths that form the integrated circuits, are also constantly being decreased.
The continual reduction in feature size places ever greater demands on techniques used to form the features. For example, photolithography is a conventional method of patterning features, such as conductive lines, on a substrate. The concept of pitch may be used to describe the size of these features. Pitch is defined as the distance between identical points in two neighboring features. These features are conventionally defined by spacings between adjacent features, which may be filled by a material, such as an insulator. As a result, pitch may be viewed as the sum of the width of a feature and of the width of the space separating that feature from a neighboring feature, or the distance between one edge of a feature and the corresponding same edge of the next adjacent feature. However, due to factors such as optics and light or radiation wavelength, photolithography techniques have a minimum pitch below which the particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique may limit feature size reduction.
Pitch doubling, or pitch multiplication, techniques have been proposed for extending the capabilities of photolithographic techniques. One example of a method of pitch multiplication is illustrated in FIGS. 1A-1F herein and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to FIG. 1A, photolithography may first be used to form a pattern of lines 10 in a photoresist material overlying a layer 20 of an expendable material and a substrate 30. As shown in FIG. 1B, the pattern may then be transferred by an etch step (preferably anisotropic) to the layer 20, forming placeholders, or mandrels 40. The photoresist lines 10 may be stripped and the mandrels 40 may be isotropically etched to increase the distance between neighboring mandrels 40, as shown in FIG. 1C. A layer 50 of material may be subsequently deposited over the mandrels 40, as shown in FIG. 1D. Spacers 60, i.e., material extending or originally formed extending from sidewalls of another material, may then be formed on sidewalls of the mandrels 40 by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in FIG. 1E. The remaining mandrels 40 may then be removed, leaving behind the freestanding spacers 60, as shown in FIG. 1F. The spacers 60 act as an etch mask for patterning underlying layers, as shown in FIG. 1F. Thus, where a given pitch formerly included a pattern defining one feature and one space, the same width now includes two features and two spaces. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased.
However, conventional pitch doubling processes are limited in that they cannot be reliably used to pitch double asymmetric features, for example, in a DRAM array where symmetry is broken by the removal of the passing wordline over the field region. Problems arise at an array gate patterning level since three features need to be defined on a pitch: two wordlines and a grounded gate over field. The grounded gate over field balances the pattern density as well as ensures that a linear self-aligned contact etch may be performed to form cavities for conducting plugs to the storage and bit contact active regions. Conventional pitch doubling is not effective in this instance because the pitch-doubled feature on every other patterned form does not define the correct gap for the wordline versus wordline and grounded gate. Accordingly, there exists a continuing need in the art for methods of pitch doubling asymmetric features and semiconductor structures including such sub-lithographic features.